Chip Automation and the March of Moore’s Law

Smaller, faster, cheaper. That is and has always been the mantra of the semiconductor industry, translating to smaller, smarter devices for all of us. In an age of mobility, add lower power to the mantra. And as we bring more autonomous vehicles into our lives, add more accountability as well.

The demands keep rising, and the industry keeps delivering. Chipmakers are exploring new ways to automate and control their processes to continue with the relentless push known as Moore’s Law.

Most people have heard of Moore’s Law and understand its effects in at least general terms. We’re all beneficiaries of Intel co-founder Gordon Moore’s famous observation in nearly every technological aspect of our lives. It can be stated in a number of ways: Technically, it’s the doubling every couple years of the number of transistors on an integrated circuit (IC); Intel’s David House stated it as the doubling of chip performance every 18 months; or you can look at it from a more economic perspective, with each IC generation seeing a doubling of computing capabilities for the same cost of production.

However you slice it, for more than half a century, Moore’s Law has been the driving force behind producing more for less—decreasing the manufacturing cost per function and enabling the production of more complex circuits on a single semiconductor substrate. Smaller, faster, cheaper.

“We have to continue to pursue relentless cost reduction, or else the technology will not be manufacturable,” commented Carolin Seward, vice president of Intel’s Technology and Manufacturing Group and director of Intel’s global supply management, at an event earlier this year.

For the automation industry too, the astonishing amount of computing power that can be squeezed into ever smaller devices has meant—in a nutshell—smaller, faster, cheaper, more capable controllers and other devices.

But what automation takes, it gives in return—so much so that it can be easy to take Moore’s Law for granted. Despite automation’s benefits, the enormous pressure the semiconductor industry faces to keep up the pace should not be underestimated.

Many complicated steps
The process of making an IC is hugely complex—unlike any other industry. Though the manufacturing of most goods can be neatly categorized as discrete or process manufacturing, semiconductor manufacturing is both. Like process manufacturing, the output of one step becomes the input of the next; like discrete manufacturing, a set of steps ends with a single product.

To describe the process on an extremely basic level, a semiconductor begins with the wafer (typically cut from highly purified silicon), which acts as a substrate for the bare chips. Before that wafer is cut into individual die to be packaged, it goes through several steps in varying sequences, including deposition, patterning, diffusion, doping, etching, polishing, metallization and others. There’s testing along the way, including at the wafer level and die level, as well as after the die is encapsulated into a package.

But part of what makes the entire process particularly complex—aside from the pure science of creating hundreds of thousands of transistors in the cross-sectional width of a single human hair—is that there are many possible outcomes for any given die on a wafer, depending on performance grading, programmability and how it will be packaged.

“Each IC in a given fab will have a different flow through the factory,” says Damon Turley, industry segment lead at Festo. “There are all these spaghetti strings in the factory, and it’s totally convoluted.”

Automate the tool, not the fab
In the early 2000s, the industry began a relatively painful transition from 200 mm (8 inch) to 300 mm (12 inch) wafers. The increased size and weight of the wafers introduced ergonomic issues that necessitated a more automated way of moving batches of wafers through the fab. The front opening unified pod (FOUP) was introduced for carrying the wafers, which not only maintained its own high level of cleanliness, but also enabled automatic transport with an overhead hoist transfer (OHT) system.

For 200 mm wafers, it’s common to use unsealed cassettes to move the wafers around the fab. Typically, employees carry the cassettes from machine to machine, often pushing them on what are referred to as shopping carts.

Though the state-of-the-art fabs are those processing 300 mm wafers, Turley contends that the older 200 mm machines are where the opportunities are for ratcheting up the automation game.

Because the entire semiconductor process is so convoluted, it’s too difficult for a manufacturing execution system (MES) to keep up with everything, Turley says. He recalls a situation in a fab that had four tungsten etch tools on site and was installing a fifth. The fifth tool had improvements made to the RF generator, resulting in better power and a better etch rate. But the MES couldn’t deal with differences between tools, he says; ultimately, they had to move the generator further away from the tool to bring its performance down to the level of the other four tools. “MES can’t make those adjustments for human excellence,” he says.

Which is one reason why Festo—which supplies products and systems throughout the process, with a concentration on valves and motion—is focused on automating at the individual tool rather than the overall fab. “The big factory isn’t stabilized yet,” Turley says. “How do you automate something that’s not stabilized? Until those things get up and stable, how can you automate between the tools?”

There’s also a shift in focus to start thinking about upgrading older tools—a major sea change in the semiconductor industry. Unlike traditional machine tool manufacturers, where much of the money is made from machine upgrades and tooling, OEMs serving the semiconductor industry depend heavily on each new machine shipment, Turley says. A lot of R&D money goes into each piece of equipment and the OEMs foot the bill, he adds.

Customized chips
The 300 mm wafer fab has been automation heavy, with lots of inter- and intra-tool automation designed for lights-out production. The problem with that approach today is that the semiconductor industry faces the exact same trend seen in so many other industries—increasing demand for customized products with smaller lot sizes.

The semiconductor industry these days, Turley says, is the application-specific IC (ASIC). “Each one of the ICs gets more and more tailored,” he says. “Instead of getting longer runs, we’re getting shorter product runs.”

No longer is it common to make cookie-cutter chips over and over again. As recently as 2010, BMW was asking for a large quantity of just five different chips to be made over a seven-month period so that it wouldn’t have to get chips made on an as-needed basis. Now, automotive suppliers like Bosch are talking about putting 50 different MEMS devices on a car, just for sensor technology, Turley says.

It’s the 200 mm fabs that can handle that flexible dynamic, Turley says, because they don’t have rigid inter- and intra-tool automation.

Robots can be problematic in a semiconductor fab, where the floors are typically perforated so that particles don’t backstream and contaminate wafers. “If you put a big robot, about 400 lbs, into the fab, you’ll produce a harmonic in the perforated floor that will cause a process shift,” Turley says.

But there’s a big opportunity to add automation to existing 200 mm equipment—with the use of Standard Mechanical Interface (SMIF) pods, which are similar in concept to the FOUPs used with 300 mm wafers. The box not only provides a mini environment for the wafers, with controlled airflow, but also pairs with automated mechanical interfaces on production equipment.

In addition to working with industry association SEMI on particle standards, Festo is working with OEMs and chipmakers to upgrade old production tools, Turley says. The machine builders typically have proprietary controls in the mini environments, and Festo works to create a blended automation system—whether electronic or pneumatic, and with anyone’s controllers, Turley says.

Standardization
With increasingly fluctuating consumer demands, manufacturing becomes ever more complex, according to Seward. Intel needs to recognize where it wants to keep things standard, and where it makes sense to add customization. “Customization comes with a lot of costs and a lot of problems in manufacturing,” she says. “We want to minimize that for competitive advantage.”

In an industry marked by custom technologies, it pays for a chipmaker like Intel—which sells hundreds of millions of microprocessors a year—to standardize production. “We’re trying to make sure we’re using standard off-the-shelf equipment and materials as much as possible,” Seward says.

Intel has actually taken the act of standardizing from one location to another to an extreme. Copy Exactly is Intel’s philosophy, implemented in the mid-1980s, to standardize production across multiple factories—perfecting processes and then duplicating them down to the last detail in fabs around the world. Each step in the process flow faces very tight tolerances, with complex interactions between steps—a complexity that only increases with each new chip generation.

So Intel’s Copy Exactly methodology is designed to keep everything as consistent as possible to keep yield up. As meticulous as duplicating the brand and color of paint in a fab, lest a different color outgas a different mix of contaminants, you can be sure that Intel demands consistency in the computers running its fab equipment.

“We build a computer, and there’s maybe 20 main components. We can’t change anything,” says Jerrold Muscolo, field sales engineer for Advantech. “If you want to supply to Intel, you have to be copy exact. It’s their methodology, their culture.”

Though Advantech supplies PCs only to the OEMs, it’s still Intel calling the shots, Muscolo says. So Advantech doesn’t change a single chip on the computer without advanced notification and plenty of documentation. “Things are going to change; it’s inevitable. But you have to control it,” he says. “You have to do this planning for obsolescence.”

“Smaller, faster, cheaper” is not necessarily the mantra for the rack-mount computers serving semiconductor equipment. In this case, it’s “quality, longevity, performance,” Muscolo says.

Dealing with the data
You can imagine that with the complexity of the processes, the semiconductor industry is working with huge amounts of data.

Data is always a big deal in semiconductor test, says Joey Tun, principal market development manager in semiconductor test for National Instruments (NI). He points in particular to work NI did with Qualcomm, a chipmaker that specializes in wireless technologies.

The challenge that Qualcomm was facing was with its newest Atheros chip—a three-radio multiple input, multiple output (MIMO) transceiver for the latest Wi-Fi standard. As wireless standards become more complex, the number of operational modes for the devices increases exponentially. For the 802.11ac wireless standard, Qualcomm added new modulation schemes, more channels, more bandwidth settings and additional spatial streams to Atheros. Characterizing wireless local area network (WLAN) transceivers is particularly challenging when faced with thousands of independent operational gain settings.

Qualcomm was looking for a way to keep WLAN test costs low and accuracy high while reducing characterization times. The answer came in the form of NI’s PXI vector signal transceiver (VST) and LabView FPGA module, combined to make a customized, flexible WLAN test system that reduced test time 200X over previous rack-and-stack instruments, resulting in lower test costs and better device characterization.

Traditional rack-and-stack measurements are limited to best estimate gain table selections. Because of test time improvements, Qualcomm could characterize the chip’s entire range of radio operation in one test sweep per device to acquire all 300,000 data points and better determine optimal operational settings. The availability of this data gave the Qualcomm team a view of the device operation they hadn’t seen before, enabling them to explore new operational regimes.

Wafer-level reliability testing is typically done on a subset of the wafers. “The test structure gives you data and is supposed to represent your entire population,” Tun explains. “So the statistical significance is extremely important.” There are hundreds of source measurement unit (SMU) channels, he adds, making data velocity critical.

For reliability, multiple thousands of sites are being probed at once. “You don’t have to move the needle very much to get a lot of data,” Tun says.

Big analytics tools are starting to come online for back-end data, with history, current trend of data, and some kind of prediction for the future, Tun says. “There’s a lot of machine learning, with artificial intelligence probably coming online soon,” he adds.

The production floor is filled with functional testers. “There’s a massive amount of data being flowed through these testers to a server,” Tun says. “That data is very much being analyzed to the extent that they can tell a lot of things from the past data. And while a test is running, before it’s even complete, if a parameter is giving them a certain value, they can predict what the rest of the test is going to be.”

Traceability
Manufacturers are finding a growing need to be able to save all kinds of test and production data in case of a chip failure somewhere down the road.

Much like traceability in the pharmaceuticals industry, traceability in semiconductors is becoming more and more important as well, especially in the automotive industry as autonomous vehicles come closer to reality. “They’ve got to keep a record of how to remake the chip in case there’s a crash,” Turley says. “As these devices take on more and more of what a car does, they’ll have to be able to rebuild the IC.”

Tun agrees: “That data traceability is going to be important for technical and legal reasons,” he says. And not just for self-driving cars. “I could see a world in which you might have a phone in your hand, and for every chip on your phone, there will be data traceability all the way back to the die.”