The chipset also makes possible designs that can receive two different video inputs simultaneously, as well as applications that can copy and distribute (simultaneously replicate) one video stream into two. Demands for higher resolution and/or higher frame rate cameras require MIPI CSI-2 output, which are limited to a short transmission range of approximately 1 foot. THCV241A serializes up to four lanes of MIPI CSI-2 signals and converts it into one or two lanes of V-by-One HS (developed and owned by THine). The THCV242 chip deserializes up to 2 V-by-One HS lanes back to the original MIPI CSI-2 signal. V-by-One HS technology supports up to 4 Gbps per lane which is robust enough to extend the transmission of 1080p60 2Mpixel uncompressed video for greater than 15 meters with typical cables. THCV241A’s 2 lanes of V-by-One HS supports up to an 8 Gbps data rate with the capability to use the second V-by-One HS lane to support data copy and distribution (replication) applications. Mirrored video signal redundancy that is supported by this chipset can be used for troubleshooting system problems or for applications such as agricultural robotics and 3D surgical equipment which require a secondary application processor that is distant from the source video camera. Also, any applications that require cameras far from host processors can utilize the features of this chipset.
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THine Electronics, Inc.
www.thine.co.jp/en/
