Sercos IP Core Now on FPGAs and SoCs

Nov. 26, 2014
The move to embed ever more industrial automation capabilities continues to pick up speed with the Sercos III protocol now available on Altera Cyclone chips.

I’ve been writing about this topic more than I expected over the past couple of years, as I did not expect the heavy flurry of activity in embedded automation technology that has occurred (see my recent column on this). Most of my coverage in this space has focused on the capabilities being designed into FPGAs and system on chips (SoCs) to enable them to handle critical automation tasks that required a multitude of independent devices just a few short years ago.

The most recent news on this front comes from Sercos International, the provider of the Sercos automation bus, which announced that it has made the Sercos III IP Core available for Altera’s low-cost, low-power Cyclone V devices. The IP core can be used on Sercos III master and slave controllers (SERCON100M/S) and includes all hardware functions such as timing, synchronization and processing of cyclic and non-cyclic data on the basis of two integrated Ethernet MACs. According to Sercos International, this move allows Sercos III master and slave devices to be implemented as a single chip solution using either Cyclone V FPGAs or Cyclone V SoCs, which integrate an ARM dual-core Cortex-A9 processor.

"The Cyclone V SoC, with its integrated ARM processor, delivers significant performance improvements for computing-intensive applications,” says Christoph Melzer, managing director of Cannon-Automata, a distributor of industrial automation products, and supplier of support and services. “For example, complete Sercos master devices can be implemented in the form of a single-chip solution.”

Detailed documentation on the IP core, reference designs and example Ethernet interface diagrams are available from Sercos International.

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