National Instruments: High-Level Synthesis Technology Improves FPGA Design Productivity
Sept. 1, 2012
The new LabVIEW FPGA IP Builder software add-on incorporates high-level synthesis (HLS) technology to accelerate system design through increased abstraction.
The add-on uses Xilinx Vivado High-Level Synthesis technology to simplify high-performance field-programmable gate array (FPGA) algorithm design and enhances productivity by reducing the need for manual optimization of high-performance algorithms. Instead, users specify functional behavior along with design constraints and the software automatically generates a hardware implementation to meet requirements. The add-on tightly integrates with LabVIEW and the LabVIEW DSP Design Module, which helps researchers and system designers in the RF and telecommunications space quickly create communication links and multirate digital signal processing (DSP) algorithms on FPGAs. Features include increased FPGA design abstraction for enhanced productivity, improved algorithm performance and resource utilization, separation of code and design constraints facilitates IP reuse and seamless deployment to NI FPGA-based devices and integration with I/O.
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